Systems-on-Chip (SoC) based on FPGA and dual-core processors are characterized by its low-cost along with a huge versatility to implement different concurrent tasks and critical activities such as hard real time hardware control and high performance multichannel data acquisition, processing and transmission. These remarkable features make SoC devices very attractive for frontier scientific applications.
- Modern Digital Design
- FPGA Technology
- VHDL for Modeling, Simulation and Logic Synthesis
- Embedded C Programming
- SoC Design Methodology
- SoC Architecture, Functional Blocks and External Interfaces
- HW/SW System Design
- High Level Synthesis
- Data Acquisition, Processing and Transmission
- SoC Trends and Advanced Scientific Applications
- Laboratory Sessions for Hands-On Training and Experimentation
Dr. Cristian Sisterna (Universidad Nacional de San Juan, Argentina). Digital Design Engineer with expertise in complex FPGA designs, Pre-Silicon and Post-Silicon validation, Functional verification, Test-Bench development, Gate Level Simulation. Very familiar with Xilinx Development Tools and FPGA devices.
Master of Technology in Computer Engineering. Arizona State University, August 1998. Honors: Phi Kappa Phi National Honor Society, Tau Alpha Pi National Honor Society. PhD Student at Arizona State University, from March 2001 to June 2007.
Sept 1998-Feb 2001; January 2008 – Present: National University of San Juan. Argentina. Associate Professor. School of Engineering. Department of Electronics. Teaching “Digital Systems I” and “Digital Systems II” and “Advanced Digital Design with VHDL”.
January 2003 – May 2003: Arizona State University. Mesa, Arizona, USA. Associate Faculty. Department of Electronics and Computer Engineering Technology. Taught CET486 and CET 586: “Hardware Description Languages: VHDL”.
November 2009 – Present: C7 Technology, San Juan, Argentina. Director: VHDL and Verilog Training Courses. Official ALTERA Training Partner for all Latin America.
November 2006 – December 2007: Marvell Technology. Chandler, Arizona. USA. Hardware-FPGA Engineer: Lead for the CSI protocol implementation in FPGA project. Other task similar to the Intel’s.
August 2005 – November 2006: Intel Corporation. Chandler, Arizona. USA. Hardware-FPGA Engineer: Pre-Silicon and Post-Silicon debug/validation. Verilog and VHDL RTL code developer, code reviewer and code debugger. Xilinx FPGAs.
October 2001 – July 2005: Lattice Semiconductor. Scottsdale, Arizona. USA. Field Application Engineer: VHDL and Verilog RTL code. Customers on-site trainings. Develop of training materials and conduct training courses and seminars.
Director of “Development of a Portable Register System with Analog, Digital, Optic and Wireless Interface”. UNSJ 2010-2013.
Participant in “Low Cost Platform for Environment Monitoring and Precision Agriculture”. UNSJ 2010-2013.
Co-Director of “Development and Implementation of a Wireless System for Ambulatory Monitoring of Biomedical Signals in High Risk Patients”. PICTO-UNSJ 2008-2013.
Participant of “Reconfigurable Virtual Instrumentation”. The Abdus Salam International Centre for Theoretical Physic” (ICTP), Trieste, Italia. Current.