Participants for this course must be bring their oun laptop with software installed.

Tutorial to install the software can be find in this link.

Files to use during the course in this link.

Minimum Content

– Introduction to Verilog.
– Combinational, sequential and complexes circuits.
– Binary representation, fixed point and floating point.
– Temporal diagrams of combinational and sequential circuits.
– Examples combining basic elements to form other complex elements.
– Timing of the circuits.
– Synchronous circuits and delay of the gates.
– Characteristic times of the FF.
– Implementation of basic circuits in FPGA.

Teaching Team

Dr. Ing. Ariel L. Pola (Clariphy-Fundación Fulgor) was born in Rio Cuarto, Argentina, in 1983. He received the Telecommunication Engineer degree from the Universidad Nacional de Rio Cuarto, Argentina, in 2008 and his Ph.D degree in engineering from the Universidad Nacional del Sur, Bahia Blanca, Argentina from 2016.

In 2009 he obtained a doctoral scholarship from the National Agency for the development of his thesis on “Reduced Complexity Architectures for Electronic Compensation Dispersion in High Speed Communications Systems” and in 2016 obtained the title of PhD in Engineering from the Universidad Nacional del Sur.

Since 2012, it has actively participated in the organization of the Argentine School of Micro-Nanocelectronics, Technology and Applications (EAMTA) and its associated CAMTA conference, whose objective is to promote the area between undergraduate and graduate students of the country and the region.

During 2009 to 2014 he collaborated in ClariPhy Argentina SA in the design and implementation of digital blocks for generations of chips for fiber optic systems from 10 Gbps to 600 Gbps.

Between 2013 and 2015, he collaborated in Fundación Fulgor in the development of a prototype for a Satellite Proximity-1 Modem for the SARE’s mission to the Comisión Nacional de Actividades Espaciales (CONAE).

He is currently member of the research staff at ClariPhy Argentina SA and Fundacion Fulgor. His research interests include high-speed architectures analysis for digital communication receivers, digital signal processing, and implementation of communication systems in ASIC and FPGA.


Ing. Federico Zacchigna (FIUBA) has a degree in Electronic Engineer from the Engineer Faculty of the the University of Buenos Aires (2012), and aspiring to the title of PhD. in Engineering by the University of Buenos Aires. He is a lecturer in the Semiconductor Devices course in the electronic engineering career at FIUBA and is a lecturer in the FIUBA embedded systems specialization course.

He has participated in several projects as integrande of the Laboratory of Embedded Systems and has dictated several courses in Digital Systems for companies and in different congresses and symposiums.



Raul Sánchez is student of electrical engineering at the Catholic University of Córdoba. He collaborated within the research group of the Communications Laboratory and Sensor Network.
Between 2013 to 2016, he collaborated in research activities as a member of the Fulgor Foundation. He worked as a consultant in the group of microelectronics and analog design in the area of design verification and integrated systems.
Since 2017, it is actively involved in the development of communications equipment to Fiber Optics developing the tasks of hardware design, implementation of architectures in FPGA and embedded systems. In addition, he integrates the research and development group in the area of artificial intelligence.